설명
설명 없음환경 설정
Si02/TEOS -Process: SiO2-SiN- PSG-BSG-BPSG -SMIF: No -Aligner: No -Loaders: One arm robot -Sensors: Wafer detection – cassette door closed -Gas box: 8 stick -Configuration of each process module: One process chamber (SiO2-SiN- PSG-BSG-BPSG) -SW Version: 4.31OEM 모델 설명
The Novellus Concept-One is a PECVD tool that uses plasma-enhanced chemical vapor deposition to deposit various dielectric films on silicon wafers. It can deposit oxide, nitride, oxynitride, PSG and TEOS oxide films. The Concept1 is also a PECVD tool that deposits dielectric films on 6" wafers. It is capable of depositing thick films in excess of 1 um and allows CMOS compatible metals, making it suitable for backend processes. The system deposits on multiple wafers in parallel in a batch-type reactor.문서
문서 없음
LAM RESEARCH / NOVELLUS
CONCEPT ONE "C1"
검증됨
카테고리
PECVD
마지막 검증일: 30일 이상 전
주요 품목 세부 정보
조건:
Used
작동 상태:
알 수 없음
제품 ID:
114673
웨이퍼 사이즈:
6"/150mm
빈티지:
1990
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
유사 등재물
모두 보기
LAM RESEARCH / NOVELLUS
CONCEPT ONE "C1"
카테고리
PECVD
마지막 검증일: 30일 이상 전
주요 품목 세부 정보
조건:
Used
작동 상태:
알 수 없음
제품 ID:
114673
웨이퍼 사이즈:
6"/150mm
빈티지:
1990
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
설명
설명 없음환경 설정
Si02/TEOS -Process: SiO2-SiN- PSG-BSG-BPSG -SMIF: No -Aligner: No -Loaders: One arm robot -Sensors: Wafer detection – cassette door closed -Gas box: 8 stick -Configuration of each process module: One process chamber (SiO2-SiN- PSG-BSG-BPSG) -SW Version: 4.31OEM 모델 설명
The Novellus Concept-One is a PECVD tool that uses plasma-enhanced chemical vapor deposition to deposit various dielectric films on silicon wafers. It can deposit oxide, nitride, oxynitride, PSG and TEOS oxide films. The Concept1 is also a PECVD tool that deposits dielectric films on 6" wafers. It is capable of depositing thick films in excess of 1 um and allows CMOS compatible metals, making it suitable for backend processes. The system deposits on multiple wafers in parallel in a batch-type reactor.문서
문서 없음